This invention relates to bucket-brigade circuit of the type known from the article published on pages 131 to 136 in the "IEEE Journal of Solid-State Circuits" for June 1969. Such bucket-brigade circuits comprise a plurality of stages which are all of the same kind, and each of which consists of a transistor and a capacitor arranged between the gate and the drain terminal thereof, and which are in such a way connected in series that the drain terminal of one transistor is connected to the source terminal of the next transistor. The gate terminals of the even-numbered transistors are controlled by a first square-wave clock signal, and the gate terminals of the odd-numbered transistors are controlled by a second square-wave and equal-frequency clock signal whose effective pulses fall within the intervals of the effective pulses of the first clock signal. Such bucket-brigade circuits are also referred to as shift registers or delay lines for analog signals.
The problem inherent in such bucket-brigade circuits has been described, for example, in the article published on pages 941 to 950 in the "IEEE Transactions on Electron Devices" for October 1971, and on pages 391 to 394 of the "IEEE Journal of Solid-State Circuits" for December 1971, and resides in the fact that the signal to be delayed is more and more attenuated as the frequency increases, reaching the greatest attenuation at the maximum delayable signal frequency which, according to the sampling theorem, is equal to half the frequency of the clock signals. The jump in potential appearing from stage to stage is the greatest at this particular frequency, while the potential jumps and consequently, the signal attenuation decrease as the signal frequency decreases. The frequency-dependence of the attenuation restricts the maximum utilizable number of stages of the bucket-brigade circuits and, consequently, also the maximum obtainable delay time.
From the first of the aforementioned publications so-called level regenerating circuits have become known which, however, only vary the d.c. level and/or amplify the signal to be delayed without preferentially raising the high frequency end thereof.